The present invention relates to a preset circuit for a clocked flip-flop.
A preset function is usually added to a clocked flip-flop so as to an initial condition independently of the clock signal. This can be realized by providing the flip-flop with preset terminals for setting and resetting, which are independent of the clock signal, in addition to the set and reset terminals, which are synchronized with the clock signal. This type of flip-flop which can be preset is labeled as set priority type or reset priority type depending upon whether a "1" or a "0" preset state appears at the output thereof when both of its preset terminals are enabled.
FIG. 1 shows the conventional JK flip-flop and its preset circuit, the flip-flop being of set priority type and having a set terminal S and an inverted reset terminal R both being intended for preset function. The flip-flop 10 comprises NOR gates 12, 14, 16, and 18, AND gates 20, 22, and 24, clocked inverters 26, 28, 30, and 32 and an inverter 34. Inputs K and J are supplied to the NOR gare 12 and AND gate 20, respectively, and output Q is generated from the inverter 34. The set input S and inverted reset input R are supplied to the NOR gates 16, 18 and AND gates 22, 24, respectively. The preset circuit comprises a NOR gate 42, an AND gate 44 and an inverter 46. Clear and load inputs are supplied to the NOR gate 42, whose output is supplied, as the inverted reset signal R, to the flip-flop 10. The clear input is supplied through the inverter 46 to the AND gate 44. A preset data input Din and the load input are also supplied to the AND gate 44, whose output is supplied, as the set signal S, to the flip-flop 10.
Prior to describing the preset operation of this flip-flop 10, the truth table of the flip-flop will be shown below as Table 1.
TABLE 1 ______________________________________ J K S .sup.--R Q.sub.n+1 Mode ______________________________________ 0 0 0 1 Q.sub.n Normal 0 1 0 1 0 1 0 0 1 1 1 1 0 1 .sup.--Q.sub.n * * 0 0 0 Reset * * 1 0 1 Set priority * * 1 1 1 Set ______________________________________ Mark * in J, and K columns represents either 0 or 1.
Q.sub.n+1 varies in synchronism with the clock signal when under normal mode, but varies independently of the clock signal when under other modes.
A preset circuit for presetting a flip-flop of set priority type can be made simpler if the set priority de is used to preset data "1", instead of the set mode. Namely, to preset the data, the clear input is set to logic 0 level at the time of usual operation, load input to logic 1 level, and data input Din to a logic level corresponding to the data to be preset. The output of the NOR gate 42, i.e., inverted reset input R thus becomes logic 0 level and the output Q of the flip-flop becomes the same level as that of the set input S. Since the output of the AND gate 44, i.e., set input S becomes the same level as that of the data input Din, the output Q.sub.n+1 is preset with the data of the data input Din. The clear input is set logic 1 level at the time of system reset operation.
When preset is finished, the mode of the flip-flop is changed to the normal mode, but the following drawback is caused when the set priority mode is changed to the normal mode. The change from the set priority mode to the normal mode makes it necessary to change both of the set and inverted reset inputs S and R, and this can be achieved by setting the load input to and logic 0 level. The AND gate 44 is thus rendered nonconductive while the NOR gate 42 conductive. As shown in FIG. 2, however, the reset mode is entered in the course of changing from the set priority mode to the normal mode so that the output Q becomes of logic 0 level is the timing at which reset input R rises is later than the timing at which the set input S falls. This is because the timing of the set and reset inputs after the load input is changed can not be precisely controlled due to the influence of the parasitic capacity and the like. In the case where data "0" is preset and the reset mode is changed to the normal mode, the drawback is not caused because the set input S is held unchanged, i.e., of logic 0 level.
The same drawback is also caused in the flip-flop of reset priority type. FIG. 3 shows the conventional preset circuit for a flip-flop of reset priority type. A set signal intended for preset function is supplied to an inverted set terminal S of a flip-flop 50. Clear and load inputs are supplied to a NOR gate 52, whose output is supplied to the inverted set terminal S. An inverted data input Din and a load input are supplied to an AND gate 54. An output of the AND gate 54 and the clear input are supplied to an OR gate 56, whose output is supplied to a reset terminal R of the flip-flop 50. The truth table of the flip-flop of reset priority type will be shown below as Table 2.
TABLE 2 ______________________________________ J K .sup.--S R Q.sub.n+1 Mode ______________________________________ 0 0 1 0 Q.sub.n Normal 0 1 1 0 0 1 0 1 0 1 1 1 1 0 .sup.--Q.sub.n * * 1 1 0 Reset * * 0 1 0 Reset priority * * 0 0 1 Set ______________________________________
Similarly to the above, the reset priority mode is employed instead of the reset mode to preset data "0" in the flip-flop of reset priority type. To preset the data, the clear input is set logic 0 level, load input logic 1 level, and inverted data input Din an inverted level of the data to be preset. The NOR gate 52 is thus rendered nonconductive, the inverted set input S becomes of logic 0 level, and the output Q of the flip-flop 50 of a level inverse to that of the reset input R. The output of the AND gate 54, i.e., reset input R of the flip-flop 50 becomes of the same level as that of the inverted data input Din. Namely, the output Q of the flip-flop 50 becomes of a level corresponding to that of data to be preset.
The same drawback already described above is caused when the reset priority mode is changed to the normal mode. As shown in FIG. 4, the flip-flop is set to the set mode when the load input is set logic 0 level and the timing at which the inverted set input S rises is later than the timing at which the reset input R falls.
In an attempt to alleviate this drawback, the falling timing of the set input S in the case of the set priority type flip-flop and the falling timing of the reset input R in the case of the reset priority type flip-flop may be; and delayed by adding a load capacity and multistage gates to these inputs. However, this method makes the operation speed slower, which provides a problem particularly when flip-flops are multistage-connected to form a counter and the like. In addition, this method sometimes prevents reliable operation from being achieved because of difference in manufacturing conditions and wiring manners when it is integrated.